View EM39LV80070M_4065860.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

em39lv800 8m bits (512kx16) flash memory specification this specification is subject to change without further notice. (04.09.2004 v1.0) page 1 of 25 general description the em39lv800 is an 8m bits flash memory organized as 512k x 16 bits. the em39lv800 uses 2.7-3.6v power supply for program and erase. featuring high performance flash memory technology, the em39lv800 provides a typical word-program time of 14 sec and a typical sector/block-erase time of 18 ms. t he device uses toggle bit or data# polling to detect the completion of the program or erase operation. to protect against inadvertent write, the device has on-chip hardware and software data protection schemes. the device offers typical 100,000 cycles endurance and a greater than 10 years data retention. the em39lv800 conforms with the jedec standard pin outs for x16 memories. the em39lv800 is offered in package types of 48-ball fbga, 48-pin tsop, and known good dice (kgd). for kgd, please contact elan microelectronics or its representatives for detailed information (see appendix at the bottom of this specification for ordering information). the em39lv800 devices are developed for applications that require memories with convenient and economical updating of program, data or configuration, e.g., dvd player, dvd r/w, wlan, router, set-top box, etc. features ? single power supply full voltage range from 2.7 to 3.6 volts for both read and write operations ? sector-erase capability uniform 2kword sectors ? block-erase capability uniform 32kword blocks ? read access time access time: 55, 70 and 90 ns ? power consumption active current: 20 ma (typical) standby current: 2 a (typical) ? erase/program features sector-erase time: 18 ms (typical) block-erase time: 18 ms (typical) chip-erase time: 45 ms (typical) word-program time: 14 s (typical) chip rewrite time: 8 seconds (typical) ? automatic write timing internal v pp generation ? end-of-program or end-of-erase detection data# polling toggle bit ? cmos i/o compatibility ? jedec standard pin-out and software command sets compatible with single-power supply flash memory ? high reliability endurance cycles: 100k (typical) data retention: 10 years ? package option 48-pin tsop 48-pin fbga
em39lv800 8m bits (512kx16) flash memory specification this specification is subject to change without further notice. (04.09.2004 v1.0) page 2 of 25 functional block diagram x-decoder flash memory array y-decoder i/o buffers and data latches address buffer & latches control logic memory address ce# oe# we# dq15-dq0 figure 0a: functional block diagram pin assignments tsop standard tsop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 a16 v ss dq15 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v dd dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# v ss ce# a0 a1 a2 a3 a4 a5 a6 a7 a17 nc nc we# a8 a9 a10 a11 a12 a13 nc nc a14 a15 nc a18 nc nc figure 0b: tsop pin assignments
em39lv800 8m bits (512kx16) flash memory specification this specification is subject to change without further notice. (04.09.2004 v1.0) page 3 of 25 fbga a13 a9 we# a7 a3 fbga top view, balls facing down a12 a14 a15 a16 dq15 v ss a8 a10 a11 dq7 dq14 dq13 dq6 nc nc dq5 dq12 v dd dq4 nc a18 nc dq2 dq10 dq11 dq3 a17 a4 a6 a2 a5 a1 dq0 a0 dq8 ce# dq9 oe# dq1 v ss nc nc nc figure 0c: fbga pin assignments pin description pin name function a0?a18 19 addresses dq15?dq0 data inputs/outputs ce# chip enable oe# output enable we# write enable v dd 2.7 ~ 3.6 volt single power supply v ss device ground nc pin not connected internally table 1: pin description
em39lv800 8m bits (512kx16) flash memory specification this specification is subject to change without further notice. (04.09.2004 v1.0) page 4 of 25 device operation the em39lv800 uses commands to initiate the memory operation functions. the commands are written to the device by asserting we# low while keeping ce# low. the address bus is latched on the falling edge of we# or ce#, whichever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first. read the read operation of the em39lv800 is controlled by ce# and oe#. both have to be low for the system to obtain data from the outputs. ce# is used for device selection. when ce# is high, the chip is deselected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either ce# or oe# is high. refer to the read cycle timing diagram in figure 1 for further details. word program the em39lv800 is programmed on a word-by-word basis. before programming, the sector where the word is located must be erased completely. the program operation is accomplished in three steps : ? the first step is a three-byte load sequence for software data protection. ? the second step is to load word address and word data. during the word program operation, the addresses are latched on the fa lling edge of either ce# or we#, whichever occurs last; and the data is latched on the rising edge of either ce# or we#, whichever occurs first. ? the third step is the internal program operation which is initiated after the rising edge of the fourth we# or ce#, whichever occurs firs t. the program operation, once initiated, will be completed within 20 s. see figures 2 and 3 for we# and ce# controlled program operation timing diagrams respectively and figure 15 for flowchart. during the program operation, the only valid re ads are data# polling and toggle bit. during the internal program operation, the host is free to perform additional tasks. any command issued during the internal program operation is ignored.
em39lv800 8m bits (512kx16) flash memory specification this specification is subject to change without further notice. (04.09.2004 v1.0) page 5 of 25 em39lv800 device operation operation ce# oe# we# dq address read v il v il v ih d out a in program v il v ih v il d in a in erase v il v ih v il x * sector or block address, xxh for chip-erase standby v ih x x high z x write inhibit x v il x high z/d out x write inhibit x x v ih high z/d out x software mode v il v il v ih see table 3 product identification * x can be v il or v ih , but no other value. table 2: em39lv800 device operation write command/command sequence the em39lv800 provides two software methods to detect the completion of a program or erase cycle in order to optimize the system write cycle time. the software detection includes two status bits : data# polling (dq7) and toggle bit (dq6 ). the end-of-write detection mode is enabled after the rising edge of we#, which initiates the internal program or erase operation. the actual completion of the write operation is asynchronous with the system; therefore, either a data# polling or toggle bi t read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either dq7 or dq6. in order to prevent such spurious rejection, when an erroneous result occurs, the software routine should include an additional two times loop to read the accessed location. if both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. chip erase the em39lv800 provides chip-erase feature, which allows the entire memory array to be erased to logic ?1? state. the chip-erase operation is initiated by executing a six-byte command sequence with chip-erase command (10h) at address 5555h in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or ce#, whichever occurs first. during the erase operation, the only valid reads are toggle bit and data# polling. see table 3 for the comm and sequence, figure 6 for timing diagram, and figure 17 for the flowchart. any commands issued during the chip-erase operation are ignored.
em39lv800 8m bits (512kx16) flash memory specification this specification is subject to change without further notice. (04.09.2004 v1.0) page 6 of 25 sector/block erase the em39lv800 offers both sector-erase and block-erase modes. the sector- (or block-) erase operation allows the system to erase the device on a sector-by-sector (or block-by-block) basis. the sector architecture is based on uniform sector size of 2 kword. the block architecture is based on uniform block size of 32 kword. the sector-erase operation is initiated by executing a six-byte command sequence with sector-erase command (30h) and sector address (sa) in the last bus cycle. the block-erase operation is initiated by executing a six-byte command sequence with block-erase command (50h) and block address (ba) in the last bus cycl e. the sector or block address is latched on the falling edge of the sixth we# pulse, while the command (30h or 50h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. the end-of-erase operation can be determined by using either data# polling or toggle bit method. see figures 7 and 8 for timing waveforms. any commands issued during the sector or block erase operation are ignored. data# polling (dq7) when the em39lv800 is in the internal progr am operation, any attempt to read dq7 will produce the complement of the true data. once the program operation is completed, dq7 will produce the true data. note that even though dq7 may have valid data immediately following the completion of an internal program operation, the remaining data outputs may still be invalid (valid data on the entire data bus will appear in subsequent successive read cycles after an interval of 1 s). during internal erase operation, any attempt to read dq7 will produce a ?0?. once the internal erase operation is completed, dq7 will produce a ?1?. the data# polling is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector-erase, block-erase, or chip-erase, th e data# polling is valid after the rising edge of sixth we# (or ce#) pulse. see figure 4 for data# polling timing diagram and figure 14 for a flowchart. toggle bit (dq6) during the internal program or erase operation, any consecutive attempts to read dq6 will produce alternating 1s and 0s, i.e., toggling be tween 1 and 0. when the internal program or erase operation is completed, the dq6 bit will st op toggling. the device is then ready for the next operation. the toggle bit is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector-erase, block-erase or chip-erase, the toggle bit is valid after the rising edge of sixth we# (or ce#) pulse. see figure 5 for toggle bit timing diagram and figure 14 for a flowchart. data protection the em39lv800 provides both hardware and software features to protect the data from inadvertent write.
em39lv800 8m bits (512kx16) flash memory specification this specification is subject to change without further notice. (04.09.2004 v1.0) page 7 of 25 hardware data protection noise/glitch protection : a we# or ce# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection : the write operation is inhibited when v dd is less than 1.5v. write inhibit mode : forcing oe# low, ce# high, or we# high will inhibit the write operation. this prevents inadvertent write during power-up or power-down. software data protection (sdp) the em39lv800 provides the jedec approved software data protection (sdp) scheme for program and erase operations. any program operation requires the inclusion of the three-byte sequence. the three-byte load sequence is used to initiate the program operation, providing optimal protection from in advertent write operations, especially during the system power-up or power-down transition. any erase operation requires the inclusion of six-byte sequence. see table 3 for the specific software command codes. during sdp command sequence, invalid commands will abort the device to read mode within t rc . the contents of dq15-dq8 can be v il or v ih , but no other value, during any sdp command sequence. common flash memory interface (cfi) the em39lv800 contains the cfi information to describe the characteristics of the device. in order to enter the cfi query mode, the system must write three-byte sequence, same as software id entry command, with 98h (cfi query command) to address 5555h in the last byte sequence. once the device enters the cfi query mode, the system can read cfi data at the addresses given in tables 4 through 6. the system must write the cfi exit command to return to read mode from the cfi query mode.
em39lv800 8m bits (512kx16) flash memory specification this specification is subject to change without further notice. (04.09.2004 v1.0) page 8 of 25 software command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle command sequence addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 word program 5555h aah 2aaah 55h 5555h a0h wa 3 data sector erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa x 4 30h block erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h ba x 4 50h chip erase 5555h aah 2aaah 55h 5555 h 80h 5555h aah 2aaah 55h 5555h 10h software id entry 5,6 5555h aah 2aaah 55h 5555h 90h manufacture id 5555h aah 2aaah 55h 5555h 90h 0000h 0007f manufacture id 5555h aah 2aaah 55h 5555h 90h 0003h 0007f manufacture id 5555h aah 2aaah 55h 5555h 90h 0040h 0001f device id 5555h aah 2aaah 55 h 5555h 90h 0001h 0020h cfi query entry 5 5555h aah 2aaah 55h 5555h 98h software id exit 7 /cfi exit xxh f0h software id exit 7 /cfi exit 5555h aah 2aaah 55h 5555h f0h notes : 1. address format a14-a0 (hex), addresses a18-a15 can be v il or v ih , but no other value, for the command sequence. 2. dq15-dq8 can be v il or v ih , but no other value, for the command sequence. 3. wa = program word address. 4. sa x for sector-erase; uses a18-a11 address lines. ba x for block-erase; uses a18-a15 address lines. 5. the device does not remain in software product id mode if powered down. 6. both software id exit operations are equivalent. 7. refer to figure 9 for more information. table 3: software command sequence
em39lv800 8m bits (512kx16) flash memory specification this specification is subject to change without further notice. (04.09.2004 v1.0) page 9 of 25 cfi query identification string* address data data 10h 0051h 11h 0052h 12h 0059h query unique ascii string ?qry? 13h 0001h 14h 0007h primary oem command set 15h 0000h 16h 0000h address for primary extend table 17h 0000h 18h 0000h alternate oem command set (00h=none exists) 19h 0000h 1ah 0000h address for alternate oem extended table (00h=none exists) * refer to cfi publication 100 for more details. table 4: cfi query identification string1 system interface address data data v dd min (program/erase) 1bh 0027h dq7-dq4: volts, dq3-dq0: 100 millivolts 1ch 0036h v dd max (program/erase) dq7-dq4: volts, dq3-dq0: 100 millivolts 1dh 0000h v pp min (00h=no v pp pin) 1eh 0000h v pp max (00h=no v pp pin) 1fh 0004h typical time out for word-program 2 n s (2 4 =16 s) 20h 0000h typical time out for min size buffer program 2 n s (00h=not supported) 21h 0004h typical time out for individual sector/block-erase 2 n ms (2 4 =16ms) 22h 0006h typical time out for chip-erase 2 n ms (2 6 =64ms) 23h 0001h maximum time out for word-program 2 n times typical (2 1 x2 4 =32 s) 24h 0000h maximum time out for buffer program 2 n times typical 25h 0001h maximum time out for individual sector/block-erase 2 n times typical (2 1 x2 4 =32ms) 26h 0001h maximum time out for chip-erase 2 n times typical (2 1 x2 6 =128ms) table 5: system interface
em39lv800 8m bits (512kx16) flash memory specification this specification is subject to change without further notice. (04.09.2004 v1.0) page 10 of 25 device geometry information address data data 27h 0014h device size=2 n byte (14h=20; 2 20 =1mbyte) 28h 29h 0001h 0000h flash device interface description; 0001h=x16-only asynchronous interface 2ah 2bh 0000h 0000h maximum number of byte in multi-byte write=2 n (00h=not supported) 2ch 0002h number of erase sector/block sizes supported by device 2dh 2eh 2fh 30h 00ffh 0000h 0010h 0000h sector information (y+1=number of sectors; z x 256b=sector size) y=255+1=256 sectors (00ffh=255) z=16 x 256 bytes=4kbyte/sector (0010h=16) 31h 32h 33h 34h 000fh 0000h 0000h 0001h block information (y+1=number of blocks; z x 256b=block size) y=15+1=16 blocks (000fh=15) z=256 x 256 bytes=64 kbyte/block (0100h=256) table 6: device geometry information absolute maximum ratings note applied conditions greater than those listed under these ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this specification, are not implied. exposure to absolute maximum stress rating conditions may affect device reliability. temperature under bias ............................................................ ?55c to 125c storage temperature .................................................................. ?65c to 150c d.c. voltage on any pin to ground potential ............................. ?0.5 v to v dd +0.5v transient voltage (<20ns) on any pin to ground potential .......... ?2.0v to v dd +2.0v voltage on a9 pin to ground potential ......................................... ?0.5 v to 13.2v package power dissipation capability (ta=25 c)........................ 1.0w surface mount lead soldering temperature (3 seconds)............ 240 c output short circuit current * ...................................................... 50ma * output shorted for no more than one second. no more than one output shorted at a time.
em39lv800 8m bits (512kx16) flash memory specification this specification is subject to change without further notice. (04.09.2004 v1.0) page 11 of 25 operating range model name ambient temperature v dd em39lv800 0 c to +70 c 2.7~3.6v table 7: operating range ac conditions of test input rise/fall time ..................................................................... 5ns output load ................................................................................. cl=30pf for 55rns output load ................................................... .............................. cl=100pf for 70ns/90ns see figures 14 and 15 dc characteristics (cmos compatible) parameter description test conditions min max unit i dd power supply current read program and erase address input =v il /v ih , at f=1/t rc min, v dd =v dd max ce#=oe#=v il , we#=v ih , all i/os open ce#=we#=v il , oe#=v ih , 30 30 ma ma i sb standby v dd current ce#=v ihc , v dd =v dd max 20 a i li i lo input leakage current output leakage current v in =gnd to v dd, v dd =v dd max v out =gnd to v dd, v dd =v dd max 1 10 a a v il v ih v ihc input low voltage input high voltage input high voltage (cmos) v dd =v dd min v dd =v dd max v dd =v dd max 0.7 v dd v dd -0.3 0.8 v v v v ol v oh output low voltage output high voltage i ol =100 a, v dd =v dd min i oh =-100 a, v dd =v dd min v dd -0.2 0.2 v v table 8: dc characteristics (cmos compatible) recommended system power-up timing parameter description min unit t pu-read * power-up to read operation 100 s t pu-write * power-up to program/erase operation 100 s * this parameter is measured only for initial qualification and after a design or process change that could affect this parameter. table 9: recommended system power-up timing
em39lv800 8m bits (512kx16) flash memory specification this specification is subject to change without further notice. (04.09.2004 v1.0) page 12 of 25 capacitance (ta=25 c, f=1mhz, other pins open) parameter description test conditons max c i/o * i/o pin capacitance v i/o =0v 12pf c in * input capacitance v in =0v 6pf * this parameter is measured only for initial qualification and after a design or process change that could affect this parameter. table 10: capacitance (ta=25 c, f=1mhz, other pins open) reliability characteristics symbol parameter min specification unit test method n end * endurance 10,000 cycles jedec standard a117 t dr * data retention 10 years jedec standard a103 i lth * latch up 100+i dd ma jedec standard 78 * this parameter is measured only for initial qualification and after a design or process change that could affect this parameter. table 11: reliability characteristics ac characteristics read cycle timing parameters 55rec 70rec 90rec symbol parameter min max min max min max unit t rc read cycle time 55 70 90 ns t ce chip enable access time 55 70 90 ns t aa address access time 55 70 90 ns t oe output enable access time 30 35 45 ns t clz * ce# low to active output 0 0 0 ns t olz * oe# low to active output 0 0 0 ns t chz * ce# high to high-z output 15 20 30 ns t ohz * oe# high to high-z output 15 20 30 ns t oh * output hold from address change 0 0 0 ns * this parameter is measured only for initial qualification and after a design or process change that could affect this parameter. table 12a: read cycle timing parameters
em39lv800 8m bits (512kx16) flash memory specification this specification is subject to change without further notice. (04.09.2004 v1.0) page 13 of 25 55ec 70ec 90ec symbol parameter min max min max min max unit t rc read cycle time 55 70 90 ns t ce chip enable access time 55 70 90 ns t aa address access time 55 70 90 ns t oe output enable access time 30 35 45 ns t clz * ce# low to active output 0 0 0 ns t olz * oe# low to active output 0 0 0 ns t chz * ce# high to high-z output 15 20 30 ns t ohz * oe# high to high-z output 15 20 30 ns t oh * output hold from address change 0 0 0 ns * this parameter is measured only for initial qualification and after a design or process change that could affect this parameter. table 12b: read cycle timing parameters program/erase cycle timing parameter symbol parameter min max unit t bp word-program time 20 s t as address setup time 0 ns t ah address hold time 30 ns t cs we# and ce# setup time 0 ns t ch we# and ce# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp ce# pulse width 45 ns t wp we# pulse width 45 ns t wph * we# pulse width high 30 ns t cph * ce# pulse width high 30 ns t ds data setup time 45 ns t dh * data hold time 0 ns t ida * software id access and exit time 150 ns t se sector erase 30 ms t be block erase 30 ms t sce chip erase 60 ms * this parameter is measured only for initial qualification and after a design or process change that could affect this parameter. table 13: program/erase cycle timing parameter
em39lv800 8m bits (512kx16) flash memory specification this specification is subject to change without further notice. (04.09.2004 v1.0) page 14 of 25 timing diagrams read cycle ti ming diagram t rc t aa t ce t oe t olz t clz t oh t ohz t chz high-z high-z v ih data valid data valid a18~a0 ce# oe# we# dq15-0 figure 1: read cycle timing diagram we# controlled program cycle timing diagram 5555 2aaa 5555 addr t bp internal program operation starts t dh t ds t ch t cs t ah t wp t as t wph xxaa xx55 xxa0 data sw0 sw1 sw2 word (addr/data) we# oe# ce# dq15-0 x can be v il or v ih , but no other value. a18~a0 figure 2: we# controlled program cycle timing diagram
em39lv800 8m bits (512kx16) flash memory specification this specification is subject to change without further notice. (04.09.2004 v1.0) page 15 of 25 ce# controlled program cycle timing diagram 5555 2aaa 5555 addr t bp internal program operation starts t dh t ds t ch t cs t ah t cp t as t cph xxaa xx55 xxa0 data sw0 sw1 sw2 word (addr/data) ce# oe# we# dq15-0 x can be v il or v ih , but no other value. a18~a0 figure 3: ce# controlled program cycle timing diagram data# polling timing diagram t oes t ce t oeh t oe data data# data# data# we# oe# ce# dq7 a18~a0 figure 4: data# polling timing diagram
em39lv800 8m bits (512kx16) flash memory specification this specification is subject to change without further notice. (04.09.2004 v1.0) page 16 of 25 toggle bit timing diagram t oes two read cycles w ith same outputs t ce t oe t oeh we# oe# ce# dq6 a18~a0 figure 5: toggle bit timing diagram we# controlled chip-e rase timing diagram six-byte code for chip-erase t sce t wp 5555 2aaa 5555 5555 2aaa 5555 xxaa xx55 xx80 xxaa xx55 xx10 sw0 sw1 sw2 sw3 sw4 sw5 ce# oe# we# dq15-0 note: this device also supports ce# controlled chip-erase operation. the we#and ce# signals are interchageable as long as minimum timings are met. (see table 14) x can be v il or v ih , but no other value. a18~a0 figure 6: we# controlled chip-erase timing diagram (see table 13).
em39lv800 8m bits (512kx16) flash memory specification this specification is subject to change without further notice. (04.09.2004 v1.0) page 17 of 25 we# controlled block- erase timing diagram six-byte code for block-erase t be t wp 5555 2aaa 5555 5555 2aaa ba x xxaa xx55 xx80 xxaa xx55 xx50 sw0 sw1 sw2 sw3 sw4 sw5 ce# oe# we# dq15-0 note: this device also supports ce# controlled block-erase operation. the w e#and ce# signals are interchageable as long as minimum timings are met. (see table 14) ba x =block address x can be v il or v ih , but no other value. a18~a0 figure 7: we# controlled block-erase timing diagram we# controlled sector -erase timing diagram six-byte code for sector-erase t se t wp 5555 2aaa 5555 5555 2aaa sa x xxaa xx55 xx80 xxaa xx55 xx30 sw0 sw1 sw2 sw3 sw4 sw5 ce# oe# we# dq15-0 note: this device also supports ce# controlled sector-erase operation. the we#and ce# signals are interchageable as long as minimum timings are met. (see table 14) sa x =sector address x can be v il or v ih , but no other value. a18~a0 figure 8: we# controlled sector-erase timing diagram (see table 13). (see table 13).
em39lv800 8m bits (512kx16) flash memory specification this specification is subject to change without further notice. (04.09.2004 v1.0) page 18 of 25 software id entry and read 5555 2aaa 5555 xxaa xx55 xx90 three-byte sequence for software id entry t wp t wph t ida t aa sw0 sw1 sw2 address a14-0 ce# oe# we# dq15-0 device id=0020h x can be v il or v ih , but no other value. 1=007fh, 2=007fh, 3=001fh 0020h 0000h 0003h 0040h0001h 12 3 figure 9: software id entry and read cfi query entry and read 5555 2aaa 5555 xxaa xx55 xx98 three-byte sequence for cfi query entry t wp t wph t ida t aa sw0 sw1 sw2 address a14-0 ce# oe# we# dq15-0 x can be vil or vih, but no other value. figure 10: cfi query entry and read
em39lv800 8m bits (512kx16) flash memory specification this specification is subject to change without further notice. (04.09.2004 v1.0) page 19 of 25 software id exit/cfi exit 5555 2aaa 5555 three-byte sequence for software id entry address a14-0 x can be vil or vih, but no other value. t wp t wph t ida ce# oe# we# xxaa xx55 xxf0 dq15-0 sw0 sw1 sw2 figure 11: software id exit/cfi exit ac input/output reference waveforms v it v ot v iht v ilt input output reference points note: v it = vinput test v ot = voutput test v iht = vinput high test v ilt = vinput low test ac test inputs are driven at v iht (0.9 v dd ) for a logic "1" and v ilt (0.1 v dd ) for a logic "0". measurement reference points for inputs and outpputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times(10% - 90% ) are <5ns figure 12: ac input/output reference waveforms
em39lv800 8m bits (512kx16) flash memory specification this specification is subject to change without further notice. (04.09.2004 v1.0) page 20 of 25 a test load example c l to tester to dut figure 13: a test load example flow charts wait options progrm/erase initiated wait t bp , t sce , t se or t be progrm/erase completed internal timer progrm/erase initiated read word read same word progrm/erase completed yes no toggle bit progrm/erase initiated read dq7 progrm/erase completed yes no data# polling does dq6 match? is dq7=true data? figure 14: wait options
em39lv800 8m bits (512kx16) flash memory specification this specification is subject to change without further notice. (04.09.2004 v1.0) page 21 of 25 word-program algorithm start load data: xxaah address: 5555h load data: xx55h address: 2aaah load data: xxa0h address: 5555h load word address/word data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed x can be vil or vih, but no other value. figure 15: word-program algorithm
em39lv800 8m bits (512kx16) flash memory specification this specification is subject to change without further notice. (04.09.2004 v1.0) page 22 of 25 software id/cfi command flowcharts load data: xxaah address: 5555h load data: xx55h address: 2aaah load data: xx98h address: 5555h wait t ida read cfi data load data: xxaah address: 5555h load data: xx55h address: 2aaah load data: xx90h address: 5555h wait t ida read software id load data: xxaah address: 5555h load data: xx55h address: 2aaah load data: xxf0h address: 5555h wait t ida load data: xxf0h address: xxh wait t ida return to normal operation return to normal operation cfi query entry command sequence software id entry command sequence software id exit/cfi exit command sequence x can be vil or vih, but no other value. figure 16: software id/cfi command flowcharts
em39lv800 8m bits (512kx16) flash memory specification this specification is subject to change without further notice. (04.09.2004 v1.0) page 23 of 25 erase command sequence load data: xxaah address: 5555h load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xxaah address: 5555h load data: xx55h address: 2aaah load data: xx10h address: 5555h wait t sce chip erased to ffffh load data: xxaah address: 5555h load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xxaah address: 5555h load data: xx55h address: 2aaah load data: xx30h address: sa x wait t se sector erased to ffffh load data: xxaah address: 5555h load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xxaah address: 5555h load data: xx55h address: 2aaah load data: xx50h address: ba x wait t be block erased to ffffh chip-erase command sequence sector-erase command sequence block-erase command sequence x can be vil or vih, but no other value. figure 17: erase command sequence
em39lv800 8m bits (512kx16) flash memory specification this specification is subject to change without further notice. (04.09.2004 v1.0) page 24 of 25 appendix ordering information (standard products) the order number is defined by a combination of the following elements. em39lv800 -70 m description package type (1 digit) m = tsop (type 1, die up, 12mm x 20mm) y = fbga (0.8mm pitch, 6mm x 8mm) h = chip form d = known good dice (for wafer dice sell) speed option (2-3 digits) 55r = 55ns 70 = 70ns 90 = 90ns ** = vdd = 2.7?3.6v **r = vdd=3.0-3.6v device number/description em39lv800 8 megabit (512k x 16-bit) flash memory 2.7-3.6 volt only read, program, and erase
em39lv800 8m bits (512kx16) flash memory specification this specification is subject to change without further notice. (04.09.2004 v1.0) page 25 of 25 ordering information (non-standard products) for know good dice (kgd), please contact elan microelectronics at the following contact information or its representatives. elan microelectronics corporation headquarters: no. 12, innovation road 1 science-based industrial park hsinchu, taiwan, r.o.c. 30077 tel : +886 3 563-9977 fax : +886 3 563-9966 http://www.emc.com.tw hong kong: elan (hk) microelectronics corporation, ltd. rm. 1005b, 10/f empire centre 68 mody road, tsimshatsui kowloon , hong kong tel : +852 2723-3376 fax: +852 2723-7780 elanhk@emc.com.hk usa: elan information technology group 1821 saratoga ave., suite 250 saratoga, ca 95070 usa tel : +1 408 366-8223 fax: +1 408 366-8220 europe: elan microelectronics corp. (europe) dubendorfstrasse 4 8051 zurich, switzerland tel : +41 43 299-4060 fax: +41 43 299-4079 http://www.elan-europe.com shenzhen: elan (shenzhen) microelectronics corp., ltd. ssmec bldg., 3f, gaoxin s. ave. shenzhen hi-tech industrial park shenzhen, guandong, china tel : +86 755 2601-0565 fax: +86 755 2601-0500 shanghai: elan electronics (shanghai) corporation, ltd. 23/bldg. #115 lane 572, bibo road zhangjiang hi-tech park shanghai, china tel : +86 021 5080-3866 fax : +86 021 5080-4600

▲Up To Search▲

Price & Availability of EM39LV80070M

	To Download EM39LV80070M Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .